Topology is computation.
Imago UniCell is a spatial FPGA compute architecture. There's no CPU, no instruction set, and no shared bus — a physical cell holds a fixed set of real hardware cores, each wired directly to its North/South/East/West neighbors. Computation happens as values arrive and propagate across that topology, one hop at a time. A timing pulse only schedules when data passes between cells; inside, the cells are unclocked, and the acknowledge handshake is what controls the flow.
What this actually is: a research project building working pieces of this architecture on real hardware, with measured numbers. It is not a general-purpose computer, and not something you can install today. Current work runs on a small Gowin FPGA board as a testbed and proof of concept, not as an accelerator.
Two hardware lines; the current one is the Tang Nano 20K
The project's first hardware line, the super carrier shell on an Arria 10 card, put every core on silicon and found that card's ceiling (roughly 200-250 cells). Work then moved to a Sipeed Tang Nano 20K (Gowin GW2AR-18, 20,736 LUT4) with a fully open toolchain: yosys, nextpnr and Apicula. The original cells proved far too large for that chip, so two stripped cell families were built for it. sub is fixed-latency with no flow control. flex is width-parameterised with a point-to-point handshake, and runs at 18 bits on the Tang.
Running on the board
A UniCell core runs on the physical Tang Nano 20K, built from source to bitstream with open tools (sequencer counting on the LEDs, 177 MHz Fmax at a 27 MHz clock).
A design, an SD card and an ESP32
A small test tool around any flex design: SD-card blocks in, results out, controlled over SPI by an ESP32. The CORDIC design runs through it on the board and matches the simulator, including a full SD round trip. WiFi control is written but not yet run on hardware.
Cells stripped to the compute
The adder went from 2,348 LUT4 to 23 (flex, 18-bit). A 100-cell 18-bit adder chain place-and-routes at 287 MHz. Cost against width is measured for every cell.
From program file to Verilog
An assembler turns a portable ICM program file into a sub or flex design. All 41 compiled test programs and a 36-cell CORDIC produce the same results as the VM and plain arithmetic.
A VM that mirrors the target
FlexGrid, the VM's flex mirror, matches the generated RTL at widths from 4 to 36 bits. About 2,190 VM tests plus the RTL-driven suites; the small-unit suites were re-run for this update.
The most recent work builds floating-point arithmetic out of ordinary cells, with no loops: a whole fp adder, parametric in the format (fp32, fp16, bfloat16). These stages are tested in generated RTL. No sub or flex design has run on the board yet; that is stated plainly on the status page.
An independent hardware research project
Imago UniCell is designed and built by a single engineer with roughly four and a half decades of computing experience, working with an AI development partner as the rest of the team. Every claim on this site is backed by a Verilog simulation, a silicon measurement, or both — nothing here is declared working without a test.