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Imago UniCell — nano/icm_v3.py / fpga/verilog/unicell_super_v1.v

One SUPER_LATCH, three real field groups

Every field position below is read directly from the live, tested encoder (nano/icm_v3.py's own CORE_FIELD_TABLES/ _ADDON_FIELDS), not transcribed from memory. Pick a core, set its fields, and watch the real 80-bit SUPER_LATCH value assemble.

All eleven ICM v3 cores (core_select 0-10, including the cross tile, #999), the add-on chain and the fine shift. Re-checked 2026-10-06 against icm_v3.encode_super_latch() on 300 random configurations. This is the ICM v3 record encoding used by the VM and the Arria 10 shells; the Tang Nano line's sub/flex cells are generated from the same records by the Flex-Sub assembler and are not configured through this latch.

Bits [4:0]
core_select live
Values 6-31 are real, reserved future headroom (#317) — the RTL's own output mux treats them as inert, not undefined.
00000
Bits [46:5]
core_config live
Reinterpreted entirely differently depending on which core is selected — this is the real, current architecture's own defining trait; the old cell had one universal topology field instead.
000000000000
Bits [66:47]
addon_config live
mask_en
shift_en
direction (0=left, 1=right)
invert_en
Identical across every core — the same addon chain, unchanged by which core_select value is active.
00000
Bits [79:0], reserved [79:69] = 0
SUPER_LATCH live
This is the exact value a real ICM v3 record's own super_latch() method would produce for these settings — the same encoder the workbench, the compiler backend, and the RTL testbenches all share.