FIG. 11 REPOSITORY
Documentation & source
Everything below lives in the project repository. Links point at the live files on GitHub, so this page never goes stale — edit the docs in the repo and this list stays accurate.
FIG. 12 KEY DOCUMENTS
- README.md Start here — what the project is, where things stand (the Arria 10 and Tang Nano 20K lines), and a quick start.
- SUPER_LATCH explainer (interactive, on this site) Pick a core, set its fields and watch the 80-bit configuration word assemble. Checked against the project's own encoder on 300 random configurations.
- docs/README.md The documentation index.
- sub/README.md The current line's cells: the sub and flex families, every cell, its measurements, and the design rules behind it.
- docs/stripped-cell/CORES_AND_WRAPPERS_REFERENCE.md Every cell generation side by side, with ports, costs and what has been proven where.
- docs/stripped-cell/ICM_V3_FORMAT.md The program format's field tables, including the target-agnostic flags (minimum width, second outputs, shift).
- docs/stripped-cell/ICM_VIX_FORMAT.md The hierarchical program format the compilers emit and the hardware assembler reads.
- docs/man/tang-nano-20k-getting-started.md Building and flashing the first deliverable onto a Tang Nano 20K.
- quickstart.py First thing to run after cloning: checks what is installed, runs a short self-test, says what to do next.
- docs/unit_bringup_guide.md The small unit (Tang Nano 20K + SD card + ESP32): loading, wiring, test ladder, WiFi control and what the board schematic says about loading new designs.
- docs/playout_capture_v1.md The unit's register map, SPI protocol, breadboard wiring sheet and measured results.
- tools/README.md The assembler (program file → Verilog) and the measurement tools.
- docs/stripped-cell/CELL_GOTCHAS.md Behaviours that will silently bite you, each one found the hard way.
- docs/stripped-cell/UNICELL_S_DSL_MANUAL.md The DSL language reference — every example compiled and confirmed working.
- docs/stripped-cell/SUPER_CELL_INTERNALS.md The Arria 10 line's super carrier shell: field maps, mechanisms, real silicon numbers.
- points/INDEX.md Sequentially numbered, append-only log of every design decision, bug found and measurement taken — split across files since it outgrew GitHub's render limit.
- nano/ The VM (including the flex mirror), program formats, tile libraries, compilers and frontends, and the workbench.
- sub/ The sub and flex cell RTL, each cell with its own self-checking bench.
- archeology/onion/ Earlier project work, preserved byte for byte and checksum-verified, not deleted.
FIG. 13 TOOLCHAIN
Open Gowin flow (current)
yosys synth_gowin, nextpnr-himbaechel-gowin, Apicula gowin_pack and openFPGALoader — synthesis to a flashed Tang Nano 20K with no vendor tools.
Icarus Verilog
iverilog -g2012 / vvp for RTL simulation — sim-first, then silicon, throughout. The generated designs are checked against the VM this way.
Python
The nano/ stack — VM, compilers, DSL, workbench. The LLVM IR frontends need llvmlite; the test suites need pytest.
Quartus Prime 25.1 (Arria 10 line)
Standard Edition on Windows, the path for the earlier Arria 10 card (IEI Mustang-F100-A10). The licence has since expired.