Nothing is declared working until it's measured

A sequencer core, configured and running, counts through its states on the board's LEDs. It is built from source with yosys, nextpnr-himbaechel-gowin and gowin_pack, and the committed bitstream reproduces byte for byte. 177 MHz Fmax against the board's 27 MHz clock, 3% of the chip. The first version stayed in reset on the real board; the cause was isolated to the reset button and removed. Why that button failed is still not known.

Any flex design can be wrapped in a test tool: an SD card (raw blocks) feeds a playout RAM, the design runs, a capture RAM collects the results and saves them back to the card, and an ESP32 controls it all over SPI. The CORDIC design runs through it on the real Tang Nano 20K: all six test angles match the simulator, and a full SD-card round trip (results saved to the card, loaded back as inputs, same answers) passes. The unit costs about 2,150 LUT4; the whole CORDIC unit is 2,556 LUT4 (12% of the chip), 4 of 46 block RAMs, 155 MHz capable at the 27 MHz clock. Bring-up took five rewires and one reseated SD card; every step is written up in the bring-up guide.

A 4-input reduction tree (about 2,333 LUT4 with the unit) and a relay chain (about 2,152) both fit the Nano and pass in simulation through the generated unit, driven only over simulated SPI; they have no bitstream yet. The Tang's S1 button now resets the unit (simulated, bitstream built, not yet pressed). An ESP32 sketch serves a password-protected web page for running the unit from a phone or laptop on the same WiFi; it is syntax-checked but has not been run on a real ESP32, and it is plain HTTP for a trusted network only. The Wasserstein engine does not fit this chip, even at its smallest size; it needs a bigger part.

The board has JTAG test points, and a route exists on paper: the ESP32 reads a bitstream from the SD card through the running unit, stores it, and sends it into the FPGA through those pads. The USB debugger chip shares the same JTAG lines, so contention is a risk. This waits for a spare board rather than risking the working one.

The original cells were too big for this chip: one carrier position is about 80% of it. So every cell was stripped to its bare compute, with no add-on chain, no cardinal routing and one dedicated port per role. sub is fixed 32-bit with exactly one cycle per cell and no flow control. flex is width-parameterised (18 bits on this chip) with a point-to-point valid/ack handshake and a global freeze. Twelve cell functions in each family, plus a merge core on flex. The adder went from 2,348 LUT4 to 23 at 18 bits, and a 100-cell 18-bit chain place-and-routes at 287 MHz.

The assembler reads a portable ICM program file as a map and generates the design as sub (statically timed, padded) or flex (handshake) hardware. It uses DSP blocks for multiplies while the card has them, and falls back to logic otherwise. All 41 programs in the compiled test corpus and a hand-built 36-cell CORDIC give the same results as the VM and as plain arithmetic, under random stalls on flex. The generators still build 32-bit designs; native-width builds are open work.

The VM now takes a data width, and FlexGrid mirrors the flex family. Each core is checked against the generated RTL at widths 4, 8, 18, 32 and 36. That work found four real RTL limits in the flex cells; three are fixed, and one (the sequencer below 8 bits) is refused with the reason.

The ICM states what a design needs (a minimum bit width, a second result word, a shift amount), and each target either provides it or refuses at compile time. Adders can now deliver their carry and multipliers their high word on a second port. A 64-bit add from two 32-bit limbs is proven in RTL.

An fp32 add and multiply are mapped onto cells in 16 stages. The carry and high-word stages, a 5-stage left-normalise with exponent adjust, sticky, round-to-nearest-even, and a 6-stage align are built with no loops and tested in generated RTL. The align uses one multiplier per stage: its high word is the shifted value and its low word is exactly the bits shifted out, which become the sticky bit. The whole adder is now assembled from cells, parametric in the format. fp32, bf16 and fp16 in generated RTL match a reference anchored to the project's float model, for normal numbers and zero. Routing it needed a new crossing tile that lets one lane pass straight over another, at one tick per tile like every other core. Special values (sub-normals, overflow, inf, nan) are next.

Every sub/flex result above is simulation, synthesis or place-and-route, not silicon. The planned host is an ESP32 (WROOM-32E) over SPI; its pins are not chosen yet. The board's role is a testbed and proof of concept, not an accelerator.

A single physical cell holding a NOR-gate logic core, RAM, an adder, an accumulator, a comparator, a latch, a sequencer, and a branch/routing core simultaneously, with the active one chosen by a runtime configuration write. 479 ALM total (301.9 ALM for the shell alone). Confirmed, across four independent measured axes (ALM, Fmax, array-scale register behavior, and placement-constraint tolerance), as the cheapest, fastest, most placement-tolerant shell version built so far — a systematic exploration of shared-storage, config-sharing, and physical-fencing ("moat") alternatives found none that beat it.

clk_div 107.05 MHz — ~4.3× margin over the 25 MHz requirement.

A systematic array-scale investigation found this card's own real ceiling: roughly 200-250 cells, 65-75 MHz Fmax at that scale — a genuine ~2.5-3× margin over the fabric clock, but not a large substrate by any real measure. Hardware exploration on this card was closed as a deliberate result. Hardware work later resumed on the Tang Nano 20K, as a testbed (FIG. 08).

A real 9th core (the command core) plus the same 8 cores above, each wrapped in a new cardinal control shell, combined into one runtime-selected cell (unicell_vix_carrier_v1.v). Real and sim-verified in both RTL and the VM, including a command core genuinely programming a fresh, never-configured neighbor end to end. No Quartus/silicon data exists for this family yet — the Quartus license expired before a real build could be run.

All of it lives in nano/. The program format is verified two independent ways — bit-for-bit against real, compiled RTL test vectors, and mechanically re-derived straight from the RTL's own comments. Four genuinely independent frontends (a purpose-built DSL, a real Python-AST parser, a real C-AST parser, and a real LLVM IR frontend that compiles real, working bounded counting loops) all produce the same shared intermediate representation. The browser workbench can drive a program, load multiple independent regions onto one shared grid, and auto-play at a chosen rate. None of this has been independently confirmed on real hardware as these specific multi-cell layouts — that distinction is kept honest, not blurred.

Earlier this card was meant to become a PCIe accelerator. That line is closed with the Arria 10 hardware work; the current plan is an ESP32 host for the Tang Nano 20K (FIG. 08).